Why does the SOF image of the Intel Agilex® 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP cause link training failure? - Why does the SOF image of the Intel Agilex® 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP cause link training failure? Description Due to a problem in the Archer City Platform (Sapphire Rapids-based CPU platform), you might observe link training failure when programming the SOF image of the Intel Agilex® 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP. Resolution This problem is not planned to be fixed in future releases of the Intel® Quartus® Prime Editon Software because it is a platform problem. To work around this problem, change the BMC of the Platform to assert the PERST when rebooting the system. Custom Fields values: ['novalue'] Troubleshooting 15012927786 False ['R-Tile for Compute Express Link Solution'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 22.4 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']