VHDL Postfit Simulation Not Supported for Arria V and Cyclone V Designs with Hard Memory Controller - VHDL Postfit Simulation Not Supported for Arria V and Cyclone V Designs with Hard Memory Controller Description This problem affects DDR2, DDR3, and LPDDR2 products using hard memory controllers. VHDL postfit simulation is not supported for Arria V and Cyclone V designs containing hard memory controllers. You will encounter VHDL elaboration errors due to unconnected ports. Resolution The workaround for this issue is to use Verilog postfit simulation. This issue will not be fixed. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']