Why does my F-Tile Ethernet Intel® FPGA Hard IP Design Example fail to pass the Quartus® Support-Logic Generation phase when using either the 200GE-8 with PTP or the 100GE-4 with PTP variants with FGT PMA? - Why does my F-Tile Ethernet Intel® FPGA Hard IP Design Example fail to pass the Quartus® Support-Logic Generation phase when using either the 200GE-8 with PTP or the 100GE-4 with PTP variants with FGT PMA? Description Due to a problem in the Quartus® Prime Pro Edition Software version 21.2, the F-Tile Ethernet Intel® FPGA Hard IP Design Example will fail to pass the Quartus® Support-Logic Generation phase with “ Error (21842): Solver failed to find a solution ”. This error is encountered when using either the 200GE-8 with PTP or the 100GE-4 with PTP variants with FGT PMA and no location constraints applied. Resolution To work around this problem for the 200GE-8 with PTP variant, make pin assignments via .qsf settings which select FGT Quads 2 and 3. For the 100GE-4 with PTP variant, make pin assignments via .qsf settings which selects FGT Quad 0. This problem has been fixed starting in version 22.2 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14014242453 True ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.2 21.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']