Why does the Generic Serial Flash Interface (GSFI) Intel® FPGA IP fail to write certain byte into the flash? - Why does the Generic Serial Flash Interface (GSFI) Intel® FPGA IP fail to write certain byte into the flash? Description Due to the limitation in the Intel® Quartus® Prime Software version 19.1 and earlier, certain byte unable to write into the flash due to unsupported byteenable patterns/cases when the GSFI IP is connected to a 64-bit Avalon master and burst data transfer is being used. Below are the unsupported GSFI IP byteenable patterns/cases: 4'b0110 4'b0111 4'b1110 Resolution To work around this problem, either send data in 32-bit width or avoid using the unsupported byte enable patterns/cases. This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 20.1. Custom Fields values: ['novalue'] Troubleshooting 1507171803 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.1 ['Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']