Can the DDR3 mem_reset_n signal be controlled by a user-accessible register? - Can the DDR3 mem_reset_n signal be controlled by a user-accessible register? Description No, there is no user-accessible register to control the state of the mem_reset_n signal. The user can assert mem_reset_n by asserting the global_reset_n or soft_reset_n inputs to the controller. The length of time the mem_reset_n is asserted active-low is under the control of the DDR3 controller. Resolution Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']