Error : Illegal constraint of DLL to the region (X, Y) to (X, Y): no valid locations in region - Error : Illegal constraint of DLL to the region (X, Y) to (X, Y): no valid locations in region Description You may experience the above fitter error when compiling a UniPHY-based memory controller in the Quartus® II version 12.1. The error occurs because there are no dedicated clock routing resources between the two PLLs. Resolution The workaround is to insert a clock buffer (altclkctrl) between the pll_ref_clk input and the PLLs. Custom Fields values: ['novalue'] Troubleshooting 1408013507 False ['PLL'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']