Need to Manually Connect Memory Model - Need to Manually Connect Memory Model Description When you attempt to generate a DDR with ALTMEMPHY design with Qsys and set the Create testbench Qsys system option to any value other than None , the system fails to connect a memory model to the Qsys-generated testbench. This issue affects all ALTMEMPHY designs targeting DDR memory devices. Simulation does not complete properly. Resolution Manually instantiate the generated memory model (<instance_name>_mem_model.v/.vhd) in the Qsys-generated testbench (<instance_name>_tb.v/.vhd) . This issue will be fixed in a future version of the DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']