Why are compilation errors in Intel Agilex® 7 device EMIF IP for VHDL design example using the Cadence NCSim* and/or the Cadence Xcelium* simulators? - Why are compilation errors in Intel Agilex® 7 device EMIF IP for VHDL design example using the Cadence NCSim* and/or the Cadence Xcelium* simulators? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.1 and earlier, you may see similar errors below when compiling the VHDL design example for Intel Agilex® 7 device EMIF IP in the Cadence NCSim* or the Cadence Xcelium* simulators. ncelab: *E,CFEPLM (sim/ip/ed_sim/ed_sim_emif_cal/altera_emif_cal_iossm_210/sim/ed_sim_emif_cal_altera_emif_cal_iossm_210_cohzsbq_arch.sv,15|60): Foreign module port calbus_rdata_1 of mode in must be associated with port/signal of entity/component ED_SIM_EMIF_CAL_ALTERA_EMIF_CAL_IOSSM_210_COHZSBQ_ARCH (sim/ip/ed_sim/ed_sim_emif_cal/altera_emif_cal_iossm_210/sim/ed_sim_emif_cal_altera_emif_cal_iossm_210_cohzsbq.vhd: line 65, position 66). ncelab: *E,CFEPLM (sim/ip/ed_sim/ed_sim_emif_cal/altera_emif_cal_iossm_210/sim/ed_sim_emif_cal_altera_emif_cal_iossm_210_cohzsbq_arch.sv,15|60): Foreign module port calbus_seq_param_tbl_1 of mode in must be associated with port/signal of entity/component ED_SIM_EMIF_CAL_ALTERA_EMIF_CAL_IOSSM_210_COHZSBQ_ARCH (sim/ip/ed_sim/ed_sim_emif_cal/altera_emif_cal_iossm_210/sim/ed_sim_emif_cal_altera_emif_cal_iossm_210_cohzsbq.vhd: line 65, position 66) Resolution The issue has been addressed starting with the Intel® Quartus® Prime Pro Edition Software v21.3. Custom Fields values: ['novalue'] Troubleshooting 14011033076 False ['External Memory Interfaces (EMIF) IP'] ['FPGA Dev Tools Quartus® Prime Software'] 21.3 20.1 ['Agilex™ FPGA Portfolio'] ['Simulation Development Tools'] ['novalue'] ['novalue']