Gated clock conversion fails due to memory - Gated clock conversion fails due to memory Hello Intel community, We use "set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON" for our prototyping system, which contains several memories (RAM, ROM). Up to now, this worked as expected. With a new component, which requires an additional RAM block, clock gate conversion fails, reason is "memory in the gated clock tree". The newly introduced memory is also listed in the mapper reports, section "Registers Packed Into Inferred Megafunctions", while all other memories are not listed here!? Does anybody has a suggestion, how to fix this problem? Thanks & best regards, Alex Replies: Re: Gated clock conversion fails due to memory Hi, Thanks for pointing out these attributes, but unfortunately they do not seem to have an impact on clock gate conversion (CGC) But I've found a solution: instead of using a single write enable (WE) for a 13 bit data word, I've used a WE for each 8 bit data slice. This seems to help the compiler to find a RAM block which is suitable for CGC Instead of: wire s_wen; assign s_wen = (~CEN) ? WEN : 1'b1; Changed to: wire [1:0] s_wen; assign s_wen = {2 {(~CEN) ? WEN : 1'b1}}; See also attached files. Regards Replies: Re: Gated clock conversion fails due to memory Hi, You may use below two settings in the QSF file. RAMSTYLE_ATTRIBUTE: https://www.intel.com/content/www/us/en/programmable/documentation/eca1490998903550.html#analysissynthesisassignmentsramstyleattribute BLOCK_RAM_TO_MLAB_CELL_CONVERSION: https://www.intel.com/content/www/us/en/programmable/documentation/eca1490998903550.html#fitterassignmentsblockramtomlabcellconversion Regards Replies: Re: Gated clock conversion fails due to memory Hi, Is it possible to prohibit the tool from using LAB memory, at least for certain instances? Regards Replies: Re: Gated clock conversion fails due to memory Hi, The tool might be placing the low density memory in the LAB elements instead of the RAM blocks. Regards. Replies: Re: Gated clock conversion fails due to memory Hi, Automatic clock gate conversion works when using a memory block generated by Quartus / qmegwiz, so far so fine. But why does it work for the attached RAM model 256x39, but not for the 64x13? Regards Replies: Re: Gated clock conversion fails due to memory Hi, Found this Note in the Intel Quartus Prime Pro Edition User Guide: Design Compilation https://www.intel.com/content/www/us/en/programmable/documentation/zpr1513988353912.html#oji1570030938918 Note: Automatic gated clock conversion supports explicit RAMs (such as WYSIWYG RAMs and Intel FPGA memory IP), but does not support inferred RAMs." This explains why clock gating did not work for the new RAM component in your design. Regards Replies: Re: Gated clock conversion fails due to memory As already described, this is an ASIC prototyping system, therefore we *need* clock gating and want to test this functionality. Replies: Re: Gated clock conversion fails due to memory The simplest (and best) solution would be to not gate your clocks. Manually put that logic on local enables or on the enable of a clock control block instead.