Why isn’t the o_rx_pcs_ready signal asserted in the simulation after applying the reset sequence for the F-tile Ethernet Altera® Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled? - Why isn’t the o_rx_pcs_ready signal asserted in the simulation after applying the reset sequence for the F-tile Ethernet Altera® Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled? Description You may see that the o_rx_pcs_ready signal will not be asserted in the simulation if you assert a reset sequencer for the F-tile Ethernet Altera® Hard IP with Auto-Negotiation and Link Training enabled before Link Training (LT) is completed on all lanes. If Link Training (LT) is enabled and is in progress, it should be completed at least once before performing any reset sequencer. Resolution Currently, there is no workaround for this, as this is expected behavior. It is recommended not to perform any reset sequence during simulation while the Auto-Negotiation and Link Training operation is in progress. Custom Fields values: ['novalue'] Troubleshooting 16024637020 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 24.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']