Why does the Quartus® Prime Standard Edition Software version 22.1 downwards show "Error (165012): The DQS pin 'dpclk' has a dual-purpose clock pin delay setting, but it is constrained to a pin at location 'PIN XX' that does not support this setting"? - Why does the Quartus® Prime Standard Edition Software version 22.1 downwards show "Error (165012): The DQS pin 'dpclk' has a dual-purpose clock pin delay setting, but it is constrained to a pin at location 'PIN XX' that does not support this setting"? Description Due to a problem in the Quartus® Prime Standard Edition Software version 22.1 downwards, an error is shown when adding the dual-purpose clock input pin delay to the DPCLK pin of the Cyclone® 10 LP FPGA. Resolution This is scheduled to be fixed in a future release of Quartus® Prime Standard Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15014506965 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 22.1 ['Cyclone® 10 LP FPGA'] ['novalue'] ['novalue'] ['novalue']