Why do HVIO pins in an Agilex® 5 or Agilex® 3 FPGA HVIO bank appear to be non-functional after device configuration? - Why do HVIO pins in an Agilex® 5 or Agilex® 3 FPGA HVIO bank appear to be non-functional after device configuration? Description In Agilex® 5 FPGA and Agilex® 3 FPGA devices that include transceivers, if the board connect the power to GTS transceiver bank and RCOMP pin left unconnected (regardless the design include a transceiver or not), while the HVIO pin is configured as input or bidirectional , high‑voltage I/O (HVIO) pins in a specific HVIO bank may fail to function after device configuration . The pins may appear stuck at high, not respond to user logic, or not transition to the expected I/O behavior. This issue does not affect the device configuration process and the device can enter user mode. This issue affects the HVIO bank adjacent to a GTS transceiver bank and is related to specific power and pin connection conditions during board design. Add the content of the new article or describe the problem or bug. Due to a product architecture requirement in Agilex® 5 FPGA and Agilex® 3 FPGA devices with GTS transceivers, the HVIO pins in the affected bank are not configured correctly during device configuration when the following pin connection condition exists. This issue occurs when ALL of the following are true : The RCOMP_GTS pin is left floating on the affected side AND The corresponding GTS transceiver power supply pins for that entire side are powered (not tied to GND) : VCCEHT_GTS connected to 1.8 V VCCERT_GTS connected to 1.0 V Under this condition, all HVIO pins in the HVIO bank adjacent to that GTS transceiver bank may appear non‑functional after configuration . Note: This issue does not occur when the RCOMP_GTS pin is properly terminated with a 499 Ω resistor. Resolution The RCOMP_GTS pin may only be left floating if the GTS transceiver power supply pins for the entire side are tied to GND . To avoid this issue, implement one of the following supported configurations : Option 1 (Recommended): Connect the corresponding RCOMP_GTS pin to a 499 Ω resistor . Option 2: Tie all GTS transceiver power supply pins on that side ( VCCEHT_GTS and VCCERT_GTS ) to GND , if transceivers on that side are not used. Additional Information Refer to the updated guidelines for Agilex 5: Pin Connection Guidelines for Agilex® 5 FPGAs and SoCs (Updated in April 2026). Related Articles Why does the high-voltage I/O (HVIO) input pin stuck at high in Agilex™ 5 FPGA devices? | Altera Community - 338218 Custom Fields values: ['novalue'] Troubleshooting QS-17888 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 26.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']