Why do I read all "zero" data from eSRAM Intel® Stratix® 10 FPGA IP intermittently ? - Why do I read all "zero" data from eSRAM Intel® Stratix® 10 FPGA IP intermittently ? Description When you tie the c<channel_number>_sd_n_0 port to a logic '1' or '0' in RTL, you might see "zero" read data from eSRAM Intel® Stratix® 10 FPGA IP. Resolution To work around this, connect signals from user logic to the c_<channel_number>sd_n_0 ports. This issue is scheduled to be fixed in future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 2209854465 False ['eSRAM IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 19.3 ['Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']