Error (10158): Verilog HDL Module Declaration error at <module_name.sv > (11): port "<interface_name>" is not declared as port - Error (10158): Verilog HDL Module Declaration error at <module_name.sv > (11): port "<interface_name>" is not declared as port Description You may see this error during synthesis in Intel® Quartus® Prime Lite Edition and Standard Editions. This error occurs when compiling System Verilog Interfaces and the port list is coded using Verilog-95 syntax. module module_a(clk, rst, module_a_inf); input clk; // Core clock input rst; // rst. module_a_to_module_b_interface.module_a module_a_inf; // Module A interface Resolution This limitation only occurs in Intel® Quartus® Prime Lite Edition and Standard Editions. There are two options to solve this: Compile using Intel® Quartus® Prime Pro Edition Change the interface syntax to: module module_a( input clk, // Core clock input rst, // rst. module_a_to_module_b_interface.module_a module_a_inf // Module A interface ); Custom Fields values: ['novalue'] Troubleshooting 14015764957 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']