Why does the RTL from my insert template not appear in the expected VHDL/Verilog HDL file? - Why does the RTL from my insert template not appear in the expected VHDL/Verilog HDL file? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 21.1 and earlier, you may see that when you insert RTL from a template into VHDL/Verilog HDL file, the content goes to another VHDL/Verilog HDL file. Resolution To work around this problem, copy the content of the template in the preview and paste it into the designated VHDL/Verilog HDL file. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.2. Custom Fields values: ['novalue'] Troubleshooting 1508904666 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 21.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']