Why does the Multi Channel DMA IP for PCI Express* for P-Tile, have incorrect bus width for the Config TL Interface? - Why does the Multi Channel DMA IP for PCI Express* for P-Tile, have incorrect bus width for the Config TL Interface? Description Due to a problem with the Multi Channel DMA IP for PCI Express* for P-Tile, in the Intel® Quartus® Prime Pro Edition software version 21.1 , the Config TL Interface reports incorrect widths. The usr_hip_tl_config_func_o signal should be a 3-bit signal, and the usr_hip_tl_config_ctl_o signal should be a 16-bit signal. Resolution This problem is fixed starting in the Intel® Quartus® Prime Pro Edition software revision 21.2. The Multi Channel DMA IP for PCI Express* user guide is scheduled to be fixed in a future release of the document. Custom Fields values: ['novalue'] Troubleshooting 14014458550, 14014542565 False ['PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 21.1 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']