Why does the Intel Agilex® 7 F-Tile device tx_pll_locked signal fail to assert when OSC_CLK_1 is used as the configuration clock source? - Why does the Intel Agilex® 7 F-Tile device tx_pll_locked signal fail to assert when OSC_CLK_1 is used as the configuration clock source? Description Due to a problem in the Intel® Quartus® Programmer version 23.3, the Intel Agilex® 7 F-Tile device tx_pll_locked signal fails to assert when the OSC_CLK_1 is used as the configuration clock source. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 23.3, install the following patch: Intel® Quartus® Prime Pro Edition Software v23.3 Patch 0.22fw for Windows (.exe) Intel® Quartus® Prime Pro Edition Software v23.3 Patch 0.22fw for Linux (.run) Readme for Intel® Quartus® Prime Pro Edition Software v23.3 Patch 0.22fw (.txt) This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 23.4. Custom Fields values: ['novalue'] Troubleshooting 15014425210 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 23.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']