HLS Coding Optimizations for Altera® Stratix® 10 Devices - 17 Minutes In this course, we will cover how the Altera® High-Level Synthesis Compiler optimizes C++ code for optimal performance on Altera® Stratix® 10 FPGAs and how to use recommended coding constructs to enable these optimizations. Most of this class covers the differences in behavior of the Altera® HLS Compiler when targeting Altera® Stratix® 10 Device with Hyperflex™ architecture when compared to earlier device families. Vast majority of the HLS coding optimizations that apply to earlier device families are still applicable to Altera® Stratix® 10 devices and are not covered in this training. Course Objectives At course completion, you will be able to: Understand how the Altera® HLS Compiler optimizes constructs for the Altera® Stratix® 10 Hyperflex™ architecture Employ coding recommendations for best performance on Altera® Stratix® 10 devices. Recommendations include 1) stream usage, 2) enable loop orchestration optimization, 3) pre-computation to reduce loop dependency feedback, 4) avoid double-pumped memories, 5) and avoid constructs that prevent new datapath control pipelining. Skills Required Familiarity with the Altera® HLS Compiler Optimization Techniques Completion of the “High-Level Synthesis Advanced Optimization Techniques” course or equivalent online trainings If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHLSS10. FPGA_OHLSS10. <p>HLS Coding Optimizations for Altera Stratix 10 Devices</p>