Why is the data link layer down on my Hard IP for PCI Express? - Why is the data link layer down on my Hard IP for PCI Express? Description Data Link Layer active reporting and Surprise Down reporting cannot be enabled for the Avalon® MM interface for PCIe Solutions in software versions 15.0 and earlier. Hence the derr_cor_ext_rpl, derr_rpl, dlup and dlup_exit signals do not indicate any useful information and should be ignored. Resolution This functionality has been added to software version 15.0.1 and later of the Quartus® II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 15.0 novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']