Why doesn't the Intel® Arria® 10 and the Intel Stratix® 10 QDR-IV IP issue burst accesses? - Why doesn't the Intel® Arria® 10 and the Intel Stratix® 10 QDR-IV IP issue burst accesses? Description Due to a problem in the Intel® Quartus® Prime software versions 18.1 and earlier, the Intel® Stratix® 10 and the Intel Arria® 10 QDR-IV IP can only support a burst length of one at the Avalon Memory-Mapped interface. This is to avoid the QDR-IV banking policy across Port A and Port B for better bus efficiency. Resolution This problem is planned to be fixed in a future version of the Intel® Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 1408426693; False ['External Memory Interfaces Arria® 10 FPGA IP', 'External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1.1 18.1 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']