*** Fatal Error: Int Divide By Zero - *** Fatal Error: Int Divide By Zero Description Due to a problem in the Quartus® II software version 11.0 and later, you may see a fatal error during synthesis if your Verilog HDL code contains a port width evaluation where either the MSB or the LSB results in a negative number. The following example code will generate this fatal error. parameter ADDR_WIDTH = 0; input [ ADDR_WIDTH-1:0] address; Resolution To work around this problem, do not create ports with a negative MSB or LSB. A future version of the Quartus II software is scheduled to report an error message describing the problem instead of producing a fatal error. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']