Incorrect ACP IDs Listed in Arria 10 and Cyclone 10 HPS Technical Reference Manuals - Incorrect ACP IDs Listed in Arria 10 and Cyclone 10 HPS Technical Reference Manuals Description The Arria V Hard Processor System Technical Reference Manual and Cyclone V Hard Processor System Technical Reference Manual list incorrect values for the HPS peripheral master input IDs in the Accelerator Coherency Port (ACP) ID mapper. The “HPS Peripheral Master Input IDs” table contains incorrect ID values. Resolution Use v14.0 or later of the Hard Processor System Technical Reference Manual . v14.0 and later show the correct ACP IDs, as follows: HPS Peripheral Master Input IDs Interconnect Master ID DMA 00000xxxx001 EMAC0 10000xxxx001 EMAC1 10000xxxx010 USB0 100000000011 USB1 100000000110 NAND 1xxxxxxxx100 DAP 000000000100 SD/MMC 100000000101 FPGA-to-HPS Bridge 0xxxxxxxx000 L2M0 0xxxxxxxx010 TMC 100000000000 ID values are binary. The letter x denotes variable ID bits that the master passes with each transaction. Custom Fields values: ['novalue'] Troubleshooting novalue True ['DMA'] ['FPGA Dev Tools Quartus II Software'] 14.0 12.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']