Why are the output clocks from my altera_pll twice the expected output frequency in simulation? - Why are the output clocks from my altera_pll twice the expected output frequency in simulation? Description Due to a problem in the Quartus® II software version 12.0 and later, Altera PLL Megafunction instances may generate PLL output clocks with twice the expected frequency when simulated. Note: This is a simulation only issue. Resolution To workaround this issue follow the steps below: Open the generated simulation model in a text editor <variation name>_sim/<variation name>.<vho/vo> Search for the text pll_vco_div Update the pll_vco_div parameter to 2 (may be incorrectly set to 1 ) For example: Verilog : <variation name>_sim/<variation name>.vo Before: <variation name>_altera_pll_altera_pll_<instance ID>.pll_vco_div = 1, After: <variation name>_altera_pll_altera_pll_<instance ID>.pll_vco_div = 2, VHDL: <variation name>_sim/<variation name>.vho Before: pll_vco_div => 1, After: pll_vco_div => 2, This problem is fxed beginning with the Quartus II software version 12.1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['FPGA Dev Tools Quartus II Software'] 12.1 12.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']