Why does simulation of the Intel® FPGA Triple-Speed Ethernet IP core fail in Mentor* ModelSim designs targeting Intel® Arria® 10 and Intel® Cyclone® 10 GX devices? - Why does simulation of the Intel® FPGA Triple-Speed Ethernet IP core fail in Mentor* ModelSim designs targeting Intel® Arria® 10 and Intel® Cyclone® 10 GX devices? Description Due to a problem with the Intel® FPGA Triple-Speed Ethernet IP designs targeting the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices may fail simulation when using the Mentor* Modelsim simulator in the Intel® Quartus® Prime Pro software version 19.1. Resolution To work around this problem, turn off optimization in the simulator by replace the " -voptargs= acc " flag in simulation script msim_setup.tcl with " -novopt " flag. This issue has been fixed starting in version 20.3 of the Intel® Quartus® Prime Pro software. Custom Fields values: ['novalue'] Troubleshooting 1409015488 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.3 19.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']