Why does a Quartus® Prime Software design that contains both the HDMI 2.0 IP and the HDMI 2.1 IP encounter a Quartus® Prime Software synthesis error? - Why does a Quartus® Prime Software design that contains both the HDMI 2.0 IP and the HDMI 2.1 IP encounter a Quartus® Prime Software synthesis error? Description Due to a problem starting from the Quartus® Prime Pro Edition Software v19.4, you may see a Quartus® Prime Software synthesis error if both the HDMI 2.0 IP and the HDMI 2.1 IP are instantiated in the same Quartus® Prime Software project. Note: HDMI 2.1 is enabled when setting Support FRL = 1 while HDMI 2.0 is enabled when setting Support FRL = 0. This problem is due to both the HDMI 2.0 IP and the HDMI 2.1 IP being generated with the same IP library file name by default. Resolution To work around this problem, edit either the HDMI 2.0 IP <design>.qip or the HDMI 2.1 IP <design>.qip files to ensure that each HDMI IP core is compiled using its own unique IP library filename. Follow the following instructions: 1. Edit either the HDMI 2.0 IP or the HDMI 2.1 IP QIP file The location of QIP file is in <Quartus_roject>/<hdmi_ip>/hdmi_ip.qip 2. Search for " -library "altera_hdmi_XXXX" " and replace all with " -library "altera_hdmi_XXXX_YY" " For example, search for -library "altera_hdmi_1961" and replace with -library "altera_hdmi_1961_20" 3. Save the modified QIP file and proceed to compile the Quartus® Prime Software project as usual. Custom Fields values: ['novalue'] Errata 1509829844 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 19.4 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']