Do Altera Devices support floating LVDS input pins? - Do Altera Devices support floating LVDS input pins? Description The following Altera® device families support floating LVDS input pins: Stratix® - series beginning with Stratix III devices HardCopy® - series beginning with HardCopy III devices Arria® - series beginning with Arria II GX devices Cyclone® - series beginning with Cyclone V devices However a 100ohm differential resistance must be applied across the P and N leg of the LVDS receiver. Internal termination can be used if available for the device family. There is no damage if the LVDS input is left floating from an undriven trace or card that is unplugged. However, you need to consider the following: Floating inputs will cause unknown switching activity leading to noise injected at the receiver and higher current consumption, all of which is design dependent and cannot be specified by Altera. It is then recommended to use external biasing schemes if the noise injection and increased current requirements are undesirable. Related Articles Do Altera devices have fail safe circuitry for differential receivers? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® III FPGAs', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'HardCopy™ III ASIC Devices', 'HardCopy™ IV E ASIC Devices', 'HardCopy™ IV GX ASIC Devices', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']