Why does Platform Designer not terminate the SystemVerilog interface input ports when using the TERMINATION port property? - Why does Platform Designer not terminate the SystemVerilog interface input ports when using the TERMINATION port property? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.4 and earlier, the HDL code generated by Platform Designer is incorrect when a SystemVerilog HDL interface input port is terminated. For example, when the following settings are applied: add_interface_port avalon_slave address address input 10 set_port_property address TERMINATION true set_port_property address TERMINATION_VALUE 0xFFFFF Platform Designer will generate the incorrect HDL code: my_ip my_ip_0 ( .bus (my_ip_0_bus), .address (10'b1111111111) ); assign readdata = my_ip_0_bus.readdata; assign my_ip_0_bus.address = address; assign my_ip_0_bus.write = write; assign my_ip_0_bus.writedata = writedata; Resolution To work around this problem, manually edit the generated HDL file (found under the <my_ip>/synth/<my_ip>.v ): my_ip my_ip_0 ( .bus (my_ip_0_bus), .address (10'b1111111111) ); assign readdata = my_ip_0_bus.readdata; assign my_ip_0_bus.address = address; assign my_ip_0_bus.write = write; assign my_ip_0_bus.writedata = writedata; assign address = 10'b1111111111; This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 22.1. Custom Fields values: ['novalue'] Troubleshooting 22012657708 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.1 20.3 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']