Why is the voltage higher than expected on VREF*_HPS pins? - Why is the voltage higher than expected on VREF*_HPS pins? Description Prior to configuration by the Preloader software, the VREF pins within the HPS section of Arria® V and Cyclone® V SoC devices will be configured with a weak pullup. If the regulator used for VREF only has the capability to source current but does not have the capability to sink current then the voltage on the VREF pins will increase and could cause the calibration sequence to fail for the external memory controller. Resolution Ensure that the regulator used to power VREF has the capability to sink and source current. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']