Why do the simulation results from Simulink not match the results from ModelSim when using Dual-Port RAM blocks? - Why do the simulation results from Simulink not match the results from ModelSim when using Dual-Port RAM blocks? Description You may experience this problem starting in Quartus® II's DSP Builder software version 11.0. This problem is seen when using the Dual-Port RAM block and selecting the Memory Block Type of MLAB in the block parameters. The problem is due to the "read_during_write_mode_mixed_ports" setting for synthesis and Modelsim® simulation being "OLD_DATA", as opposed to "NEW_DATA". Resolution To work around this issue, in the file alt_dspbuilder_dualram_xxx.vhd, change the parameter "read_during_write_mode_mixed_ports" from "NEW_DATA" to "OLD_DATA". Alternatively, if your device family has embedded memory blocks that support mixed-port read-during-write mode of OLD_DATA, for example M9K in the Stratix IV devices, you can select this Memory Block Type in your Dual-Port RAM block. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['DSP Builder for Pro Edition'] ['novalue'] ['novalue']