Why does the E-Tile Ethernet IP for Intel Agilex® 7 FPGA get stuck during 100G-PAM4 dynamic reconfiguration? - Why does the E-Tile Ethernet IP for Intel Agilex® 7 FPGA get stuck during 100G-PAM4 dynamic reconfiguration? Description Due to a bug in the E-Tile Ethernet IP for Intel Agilex® 7 FPGA, if you are using the IP reset ( i_csr_rst_n ) during dynamic reconfiguration process, " DR_busy " can get stuck, “ wait_for_ehipg_cfg_load_done ” cannot be achieved. This situation cannot be recovered by resetting the IP. Only re-downloading the FPGA image can recover the link. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 23.1 Custom Fields values: ['novalue'] Troubleshooting 15012117053 False ['E-tile Hard IP for Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.2 ['Agilex™ 7 FPGA F-Series'] ['novalue'] ['novalue'] ['novalue']