Why does the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example testbench fail to simulate correctly in the supported Siemens* QuestaSim* 2021.4 or later versions? - Why does the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example testbench fail to simulate correctly in the supported Siemens* QuestaSim* 2021.4 or later versions? Description Due to a compatibility problem between version 22.3 and later of the Intel® Quartus® Prime Software and the Siemens* QuestaSim* 2021.4, 2022.4 tool, simulation of the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example testbench will fail to simulation correctly with the following errors: # INFO: 116032 ns RP User Avmm Driver: begin RP Configuration. # FATAL: Simulation stopped due to inactivity! # FAILURE: Simulation stopped due to Fatal error! # FAILURE: Simulation stopped due to error! Resolution To work around this problem, use Siemens* Questa Sim-64 2022.2. Starting in the Intel® Quartus® Prime Software version 23.3, solve this issue by adding this command " set USER_DEFINED_ELAB_OPTIONS "-voptargs=\"-noprotectopt\" before running simulation in the Siemens* Questa Sim. Custom Fields values: ['novalue'] Troubleshooting 14017262366 False ['P-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 22.3 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['Agilex™ 7 FPGA F-Series Dev Kit', 'Stratix® 10 DX Development Kits']