Output Port Definitions Changed from Scaler to Vector Types for Avalon-ST Variants of Hard IP for PCI Express IP Core - Output Port Definitions Changed from Scaler to Vector Types for Avalon-ST Variants of Hard IP for PCI Express IP Core Description The following output ports were defined as scalar in version 14.0 of the Quartus II software: rx_st_eop, rx_st_err, rx_st_sop, rx_st_valid, tx_st_eop, tx_st_err, tx_st_sop, and tx_st_valid . These ports are defined as vectors in the 15.0 version of the Quartus II software. Resolution This change has no effect for Verilog HDL. For VHDL, you may need to redefine these ports as vectors using the std_logic_vector (0 downto 0) syntax starting in 15.0. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PCI Express'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']