Why is the clock not running in my design when I use the Clock Control Intel® FPGA IP? - Why is the clock not running in my design when I use the Clock Control Intel® FPGA IP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, you might see the clock which input to the Clock Control Intel® FPGA IP is not running. This problem occurs when you enable the Clock Enable feature in the Clock Control Intel® FPGA IP and drive the ena port low. This problem only affects designs targetting Intel® Stratix® 10 or Intel Agilex® 7 devices. Resolution To work around this problem, set the "Clock Enable Type" in Clock Control Intel® FPGA IP to Root Level. This problem is fixed beginning in the Intel® Quartus® Prime Pro Edition Software version 22.3. Custom Fields values: ['novalue'] Troubleshooting 15013697245 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 22.2 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']