Error(21843): Rule: gdrb_ip758fluxtop::ux0_cdr_postdiv_counter_range_rule @ gdr.z1577b.u_ux_quad_2.flux_top - Error(21843): Rule: gdrb_ip758fluxtop::ux0_cdr_postdiv_counter_range_rule @ gdr.z1577b.u_ux_quad_2.flux_top Description You may encounter this error during the Logic Generation stage when the F-Tile PMA/FEC Direct PHY IP is configured with a value for TX user clock div by: ( fgt_tx_pll_txuserclk_div ) or RX user clock div by: ( fgt_rx_cdr_rxuserclk_div ), such that the generated User Clock 1 value exceeds the maximum specification for the corresponding Agilex™ 7 FPGA device core frequency, as specified in the datasheet. Derived clock value formula for, TX datapath: User clock 1 = VCO frequency / fgt_tx_pll_txuserclk_div RX datapath: User clock 1 = VCO frequency / fgt_rx_cdr_rxuserclk_div where, VCO frequency is populated in the IP under ' Tx FGT PLL Settings ' and ' RX FGT CDR Settings ' Resolution Enter the value of TX user clock div by: or RX user clock div by: after evaluating the generated User Clock 1 frequency using the above formula. Example: If VCO frequency = 160000 MHz, then the minimum value of TX user clock div by: or RX user clock div by: should be 16, such that User clock 1 = 1000MHz for a -1 speed grade of device. This information is already contained within the IP user guide. A check is scheduled to be added in the IP GUI in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16026172243, 16026745866 False ['F-Tile PMA/FEC Direct PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']