XIP1183B: Balanced AES256-XTS IP Core - AES-XTS IP cores implement the Advanced Encryption Standard (AES) with a 256-bit key in XTS mode. Xiphera designs and implements hardware-based security using proven cryptographic algorithms. Our strong cryptographic expertise and extensive experience in digital system design enable us to help… Arria® 10 SX FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Cyclone® IV E FPGA Stratix® III FPGA AES-XTS IP cores implement the Advanced Encryption Standard (AES) with a 256-bit key in XTS mode. AES-XTS is a block-based encryption method primarily employed to secure data while it is stored, and the IP cores can be used to encrypt data on hard drives and other storage devices. Networking / Security Access Aerospace ASIC Proto Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Defense Government Medical Test Transportation Wireless XIP1183B: Balanced AES256-XTS IP Core Key Features Moderate resource requirements: The entire XIP1183B requires 6079 Adaptive Lookup Modules (ALMs) (Intel® Agilex® F), and does not require any multipliers or DSPBlocks2. Offering Brief No No No No Encrypted VHDL VHDL Arria® 10 SX FPGA Cyclone® IV GX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Arria® V GZ FPGA Agilex™ 9 FPGA Direct RF-Series MAX® V CPLD Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Arria® V GX FPGA Cyclone® V E FPGA Agilex™ 3 FPGA C-Series Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Cyclone® IV E FPGA Stratix® III FPGA No No 25.1.1 Offering Brief Production a1JUi0000049UR8MAM What's Included Encrypted RTL or source code Ordering Information XIP1183B a1JUi0000049UR8MAM Production Intellectual Property (IP) a1MUi00000BO8toMAD a1MUi00000BO8toMAD Select 2026-04-21T12:58:33.000+0000 AES-XTS IP cores implement the Advanced Encryption Standard (AES) with a 256-bit key in XTS mode. Partner Solutions