RapidIO II IP Core Capture Registers Might Capture Wrong Information for Out-of-Order Maintenance Response Packet With Error - RapidIO II IP Core Capture Registers Might Capture Wrong Information for Out-of-Order Maintenance Response Packet With Error Description When the RapidIO II IP core Maintenance module receives a response packet with ERROR status, it captures information about the errored packet in the Error Management Extension Logical/Transport Layer capture registers at offsets 0x314, 0x318, and 0x31C. However, if the response is an out-of-order response, the IP core might populate these registers with information from the wrong original request. More specifically, the IP core might populate the capture registers with information from the most recently transmitted request instead of information from the corresponding request with the same TID as the response packet. Resolution This issue has no workaround. This issue will be fixed in a future version of the RapidIO II MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']