How many Clock Control Intel FPGA IP for clock input muxing is available in an Intel® Stratix® 10 device? - How many Clock Control Intel FPGA IP for clock input muxing is available in an Intel® Stratix® 10 device? Description There is no definite maximum number of the Clock Control Intel® FPGA IP for clock input muxing in an Intel® Stratix® 10 device. Unlike the Clock Control Block (ALTCLKCRTL) IP in previous Intel® FPGA devices, the Clock Control Intel® FPGA IP consists of logic element when the IP is used for clock input muxing without clock gating or output division option. So the maximum number depends on device utilization and design complexity. Custom Fields values: ['novalue'] Troubleshooting 14014171421 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']