Why does phasedone always appear high after asserting phasestep? - Why does phasedone always appear high after asserting phasestep? Description Depending on the voltage-controlled oscillator (VCO) and scanclk frequencies, the phasedone low time may be greater than or less than one scanclk cycle. If you sample the phasedone signal with scanclk, you may miss the low pulse of phasedone. Resolution Related Articles What is the maximum specification of the phasedone low time? Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']