Why is the waitresponsevalid signal not exported when using the Avalon®-MM Pipeline Bridge FPGA IP when “Use Avalon Transaction Responses” option is enabled? - Why is the waitresponsevalid signal not exported when using the Avalon®-MM Pipeline Bridge FPGA IP when “Use Avalon Transaction Responses” option is enabled? Description Due to a problem in the Avalon®-MM Pipeline Bridge FPGA IP, when “Use Avalon Transaction Responses” option enabled, only writeresponse signal is exported, writeresponsevalid is not. For connections between Avalon-MM masters and Avalon-MM Pipeline Bridge, where write responses are expected by masters, the absence of writeresponsevalid signal will result in potential issues. Resolution This problem has been fixed in Intel® Quartus® Prime Pro Edition software version 20.3 and later versions. Custom Fields values: ['novalue'] Troubleshooting 1508008749,22010626385 False ['Avalon-MM Pipeline Bridge IP', 'Memory Mapped'] ['FPGA Dev Tools Quartus® Prime Software QUARTUS-ALITE', 'FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 20.3 19.4 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']