Simulation problem with Avalon-MM clock crossing bridge - Simulation problem with Avalon-MM clock crossing bridge Hi there, I'm using the avalon MM clock-crossing bridge with questasim. After generating the core in Quartus Prime, I compile it in questasim with no issues. However, in simulation, all of its output ports are stuck at X. Replies: Re: Simulation problem with Avalon-MM clock crossing bridge As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘ https://supporttickets.intel.com’ , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 5/5 survey Replies: Re: Simulation problem with Avalon-MM clock crossing bridge May I know if there is any update from previous reply? Replies: Re: Simulation problem with Avalon-MM clock crossing bridge Understood. Any testbench written for this simulation? Mind to share here if there is any. If there is any input value assigned to the input there should be a value outputted. Replies: Re: Simulation problem with Avalon-MM clock crossing bridge I found that the IP simulation model outputs X normally, after reset, until the first transaction is passed through it. Then the IP outputs stay non-X. Replies: Re: Simulation problem with Avalon-MM clock crossing bridge Are you writing any testbench? mind to share it here the snippet? and also the snapshot in the questasim. Replies: Re: Simulation problem with Avalon-MM clock crossing bridge Kindly take note that they will be some slowness on the first reply due to the public holiday, we will get back to you as soon as possible.