Do Agilex™ 5 FPGA and SoC FPGA and Agilex™ 7 FPGA and SoC FPGA M-Series support user-controlled refresh feature in EMIF IP? - Do Agilex™ 5 FPGA and SoC FPGA and Agilex™ 7 FPGA and SoC FPGA M-Series support user-controlled refresh feature in EMIF IP? Description In the External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGA and SoC and External Memory Interfaces Agilex™ 7 FPGA M-Series IP User Guide version 25.1 and earlier, you may find that the user-controlled refresh feature is available for these FPGAs. This feature is not supported in Agilex™ 5 FPGA and SoC FPGA and Agilex™ 7 FPGA and SoC FPGA M-Series. Resolution This information will be updated in future release of External Memory Interfaces IP User Guide. Custom Fields values: ['novalue'] Troubleshooting 15017699690 False ['novalue'] ['novalue'] novalue novalue ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']