Why does Intel® Quartus® software compilation fail when using the Multi-Volt feature in Intel® MAX® 10 device? - Why does Intel® Quartus® software compilation fail when using the Multi-Volt feature in Intel® MAX® 10 device? Description Error (169029): Pin uses I/O standard 2.5 V, which has a VCCIO requirement incompatible with that bank’s VCCIO setting or its other pins that use VCCIO 3.3 V. You will get this error message in the Intel® Quartus ® Prime Standard Edition Software when you place a 2.5 V input standard pin in an I/O bank powered by 3.3 V VCCIO in Intel® Max® 10. This is a Quartus® limitation and not a device limitation. It will impact the Intel® Quartus ® Prime Standard Edition Software Version that supports Intel® MAX® 10 devices. Resolution You can assign the 2.5 V input standard pin to be 3.3 V input standard to avoid errors in the software. On the hardware, the output signal driven from the upstream device to the FPGA input can be of other I/O standards with a different I/O buffer voltage supply than the FPGA input VCCIO. Please verify the VIH/VIL of the input signal is meeting the VIH/VIL of the VCCIO of the input bank. Refer to Intel® MAX® 10 General Purpose I/O User Guide for the list of supported input standards for each VCCIO and the associated design guideline about the use of the Multi-Volt feature in the Intel® MAX® 10 device. For example: You want to use the 2.5 V LVCMOS input standard in the I/O bank powered by 3.3 V VCCIO. Assign 3.3 V LVCMOS input standard to the input pin to avoid errors in the software. You can use the 2.5 V LVCMOS output standard on the hardware to interface with this input pin. On the hardware, you can use the 2.5 V LVCMOS output standard to interface with this input pin and verify the VIH/VIL of this signal is meeting the VIH/VIL of 3.3V LVCMOS. Custom Fields values: ['novalue'] Troubleshooting 15010460607 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 14.1 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']