Low Latency 40-100GbE IP Core VHDL Model Cannot Simulate Correctly - Low Latency 40-100GbE IP Core VHDL Model Cannot Simulate Correctly Description If you generate a VHDL model for a Low Latency 40-100GbE IP core, it cannot simulate correctly. Resolution This issue has no workaround. You must generate your IP core variation in Verilog HDL. This issue will be fixed in a future version of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Ethernet', 'Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1a10 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']