RapidIO II IP Core I/O Logical Layer Slave Port Requires Continuous Write Signal Assertion - RapidIO II IP Core I/O Logical Layer Slave Port Requires Continuous Write Signal Assertion Description The RapidIO II IP core I/O Logical layer slave port requires that the Avalon-MM master assert the ios_rd_wr_write signal continuously for the full duration of the incoming write burst. If the Avalon-MM master module deasserts the ios_rd_wr_write signal while it is sending write data to the RapidIO II IP core, the IP core incorrectly divides the incoming data into multiple transmitted packets on the RapidIO link. Resolution This issue has no workaround. You must ensure that all Avalon-MM master modules in your design that communicate with the RapidIO II IP core I/O Logical layer slave port, meet the requirement to assert the ios_rd_wr_write signal continuously for the full duration of any write burst to the RapidIO II IP core. This issue is fixed in version 14.1 of the RapidIO II IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 14.1 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']