Why is the reference clock frequency set incorrectly when I update the Hard IP for PCI Express? - Why is the reference clock frequency set incorrectly when I update the Hard IP for PCI Express? Description Due to a bug when you change the reference clock frequency for an existing IP Compiler for PCI Express® (PCIe), the new reference clock frequency is not updated in the transceiver used by the PCIe IP core. Resolution To work around this issue, follow these steps to change the reference clock for an existing PCIe IP variant. 1. Delete the serdes variant (<variant>_serdes.v). 2. Update the reference clock in the MegaWizard Plug-in Manager. 3. Regenerate the PCIe variant. Related Articles Why do I get the error message Error: Differential I/O output pin <name> is assigned to a non differential location <name> Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® GX FPGA', 'Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® IV FPGAs', 'Cyclone® IV GX FPGA', 'Stratix® GX FPGA', 'Stratix® II GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']