Why does the F-Tile DisplayPort Intel® FPGA IP Design Example simulation fail in the Intel® Quartus® Prime Pro Edition Software version 22.4? - Why does the F-Tile DisplayPort Intel® FPGA IP Design Example simulation fail in the Intel® Quartus® Prime Pro Edition Software version 22.4? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 F-Tile DisplayPort Intel® FPGA IP Design Example, there is a bug in the simulation model where the Rx Phy Top mimics hardware lane reversal behavior that was required by the DisplayPort FMC daughter card but the simulation testbench failed to include the same lane reversal. This causes the Rx CRC to show incorrect values. Resolution To work around this problem for the Intel® Quartus® Prime Pro Edition Software version 22.4, reverse the Tx parallel data by implementing the steps shown below: Modify the file “<project>/simulation/rtl/tx_phy/tx_phy_top.sv”. Change the below paramater: parameter LANE_POLARITY_INVERTED = 0 And add below code: assign gxb_tx_clkout = tx_ls_clkout[3]; assign tx_cadence_fast_clk = tx_syspll_clkout[3]; assign tx_parallel_data = (dp_tx_link_rate_sync < 8'd6) ? {24'd0,tx_parallel_data_i[16+:16],1'd0,tx_parallel_valid[0],22'd0,tx_parallel_data_i[0+:16], 24'd0,tx_parallel_data_i[56+:16],1'd0,tx_parallel_valid[1],22'd0,tx_parallel_data_i[40+:16], 24'd0,tx_parallel_data_i[96+:16],1'd0,tx_parallel_valid[2],22'd0,tx_parallel_data_i[80+:16], 24'd0,tx_parallel_data_i[136+:16],1'd0,tx_parallel_valid[3],22'd0,tx_parallel_data_i[120+:16]} : {20'd0,tx_parallel_data_i[20+:20],1'd0,tx_parallel_valid[0],18'd0,tx_parallel_data_i[0+:20], 20'd0,tx_parallel_data_i[60+:20],1'd0,tx_parallel_valid[1],18'd0,tx_parallel_data_i[40+:20], 20'd0,tx_parallel_data_i[100+:20],1'd0,tx_parallel_valid[2],18'd0,tx_parallel_data_i[80+:20], 20'd0,tx_parallel_data_i[140+:20],1'd0,tx_parallel_valid[0],18'd0,tx_parallel_data_i[120+:20]}; This problem has been fixed in the Intel® Quartus® Prime Pro Edition Software version 23.1. Custom Fields values: ['novalue'] Troubleshooting 15012276045 False ['DisplayPort'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']