LZ4SNP-D: LZ4/Snappy Data Decompressor - LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithms. The core receives compressed files, automatically detects the LZ4… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Arria® 10 SX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Agilex™ 9 FPGA Direct RF-Series Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Arria® V GX FPGA Cyclone® V E FPGA Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithms. The core receives compressed files, automatically detects the LZ4 or Snappy format, and outputs the decompressed data. The core features fast processing with low latency and high throughput. In its default configuration, LZ4SNP-D outputs up to 7.8 bytes of decompressed data per clock cycle and can be clocked at frequencies exceeding 1 GHz in modern ASIC technologies. Designers can scale the throughput by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps. The processing latency is approximately 30 clock cycles. The decompression core operates on a standalone basis—offloading the host CPU from the demanding task of data decompression—and has been designed for easy integration and use. No preprocessing of the incoming compressed files is required, as the core parses the file headers, checks the input files for errors, and outputs the decompressed data payload. Extensive error tracking and reporting enable the core to ensure smooth system operation and error recovery, even in the presence of errors in the compressed input files. Furthermore, internal memories can optionally support Error Correction Codes (ECC) to simplify achieving enterprise-class reliability or functional safety requirements. Filters /Transforms Consumer Industrial Transportation Wireless LZ4SNP-D: LZ4/Snappy Data Decompressor Key Features LZ4: 64KB history window size. All frame and block formats. CRC checking (optional, on request). Dictionaries not supported. Offering Brief No No No Yes Encrypted Verilog Verilog Arria® 10 SX FPGA Agilex™ 5 FPGA E-Series MAX® 10 FPGA Cyclone® V SX FPGA Agilex™ 9 FPGA Direct RF-Series Agilex™ 7 FPGA I-Series Arria® V SX FPGA Stratix® 10 DX FPGA Stratix® 10 SX FPGA Agilex™ 7 FPGA M-Series Cyclone® V GT FPGA Arria® 10 GT FPGA Arria® V ST FPGA Arria® 10 GX FPGA Stratix® 10 TX FPGA Cyclone® V SE FPGA Arria® V GX FPGA Cyclone® V E FPGA Cyclone® V GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Cyclone® V ST FPGA Agilex™ 5 FPGA D-Series Stratix® 10 GX FPGA Arria® V GT FPGA Cyclone® 10 LP FPGA Agilex™ 7 FPGA F-Series Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U6eMAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, or netlist Ordering Information LZ4SNP-D a1JUi0000049U6eMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2026-06-29T21:15:50.000+0000 LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithms. The core receives compressed files, automatically detects the LZ4 or Snappy format, and outputs the decompressed data. The core features fast processing with low latency and high throughput. In its default configuration, LZ4SNP-D outputs up to 7.8 bytes of decompressed data per clock cycle and can be clocked at frequencies exceeding 1 GHz in modern ASIC technologies. Designers can scale the throughput by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps. The processing latency is approximately 30 clock cycles. The decompression core operates on a standalone basis—offloading the host CPU from the demanding task of data decompression—and has been designed for easy integration and use. No preprocessing of the incoming compressed files is required, as the core parses the file headers, and checks the input files for errors. Partner Solutions