Altera® FPGA E-Tile Transceiver Basics - 59 Minutes Altera® Agilex ® F-Series and Altera® Stratix® 10 TX, MX and DX FPGAs contain different embedded transceivers types to support the wide range of I/O bandwidth requirements of today’s high-performance systems. This training is the first step in learning how to build a high-speed interface using E-tiles, whether your target application requires Ethernet, FibreChannel, Common Public Radio Interface (CPRI) or even your own proprietary, non-standard protocol. By the end of this training, you will be able to define the blocks found in the E-tile transceivers and how the blocks are used together to ensure successful data transfers between high-speed serial links and your FPGA core logic. You will also be introduced to a tool to help plan your use of E-tile channels called the Altera® Stratix® 10 FPGA Course Objectives At course completion, you will be able to: Describe the blocks found in the transmitter and receiver paths of Altera® Agilex™ F-Series and Altera® Stratix® 10 FPGA E-tile high-speed serial transceivers Describe how each transceiver block is used in supporting a high-speed serial interface Select the appropriate channel configuration for your design based on your high-speed protocol requirements Use the Altera® Stratix® 10 FPGA E-tile Channel Placement Tool to create a valid layout of transceiver channels for your design project Skills Required Background in digital logic General understanding of FPGA architecture If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OS101116. FPGA_OS101116. <p>Altera FPGA E-Tile Transceiver Basics</p>