Reset Timing Violation for QSPI Flash Specification - Reset Timing Violation for QSPI Flash Specification Description In Agilex™ 7 FPGA F & I-Series devices, when the SDM runs the boot ROM firmware, it takes about 800ns to reset the flash memory using the AS_nRST reset pin before reading from it. This may violate the reset timing specification from QSPI flash memory vendors Macronix, Winbond, and ISSI. Due to this, the SDM may fail to read the flash memory and may get stalled at the boot ROM phase. Resolution To workaround this problem, toggle the nCONFIG to recover from this issue and reconfigure the device. Please refer to Table 4 on the Device Configuration Support Center page for a list of third-party configuration devices tested and supported by Altera. Custom Fields values: ['novalue'] Troubleshooting 15016639470 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 23.2 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']