Why is BAR addresses greater than 32 bits truncated to 32 bits on my Hard IP for the PCI Express Avalon-MM variant? - Why is BAR addresses greater than 32 bits truncated to 32 bits on my Hard IP for the PCI Express Avalon-MM variant? Description Due to a problem with the Avalon-MM Hard IP core for PCI Express*, BAR addresses greater than 32 bits will be truncated to 32 bits only. The upper bits will be set to zero. This only affects the downstream direction Rxm ports when operating in 64-bit addressing mode. It does not affect the Txs ports or when operating in 32-bit addressing modes. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.0. Custom Fields values: ['novalue'] Troubleshooting FB: 477237; True ['Avalon-MM Arria® V GZ Hard IP for PCI Express IP', 'Avalon-MM Arria® V Hard IP for PCI Express IP', 'Avalon-MM Cyclone® V Hard IP for PCI Express IP', 'Avalon-MM Stratix® V Hard IP for PCI Express IP', 'Arria® 10 Cyclone® 10 Hard IP for PCI Express', 'PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0 16.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Cyclone® 10 GX FPGA', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']